1. Field of the Invention
This invention relates to a video signal processing device which is arranged to record a video signal by time compressing the video signal.
2. Description of the Related Art
For recording a video signal, a method of carrying out a multiplex recording operation on a luminance signal Y and a chrominance signal C by time compressing them has been known. The operating principle of this time-base multiplexing method is as shown in FIG. 1 of the accompanying drawings. In the case of FIG. 1, a time-base multiplexing operation is performed by time compressing the luminance signal Y and the chrominance signal C of each horizontal scanning period (hereinafter referred to as H period) in the ratio of, for example, M : N. With these signals Y and C recorded through the time-base multiplexing operation carried out in this manner, these signals are readily separable by means of a simple switch. Therefore, this method, as compared with a frequency multiplexing method, lessens the possibility of picture quality deterioration due to imperfect separation of the signals Y and C resulting in the so-called cross-color or cross-luminance.
FIG. 2 is a block diagram showing, by way of example, an arrangement of an electronic still picture camera to which the conventional time-base multiplex recording method is applied. In accordance with this arrangement, an image formed by an imaging lens 101A is converted by a solid-state image sensor 101B into an electrical signal for every picture element. The solid-state image sensor 101B serially produces, for every picture element, image data in synchronism with a clock signal f produced from a clock pulse generator 109. The image signal thus produced from the sensor 101B is amplified by a pre-amplifier 102 and is then supplied to a video signal processing circuit 103. At the circuit 103, a luminance signal Y and a chrominance signal C are produced mainly by a matrix computing operation. These signals Y and C are respectively supplied via switches S1 and S2 to a first or second memory 104 or 105 and a third or fourth memory 106 or 107 to be temporarily stored at these memories. Upon completion of the storing process, the connecting position of each of the switches S1 and S2 is shifted to a position for the other memory. Meanwhile, switches S3 and S4, which are disposed on the output side of these memories, are in connecting positions for the other memories. The switch arrangement is such that, while the signal Y is written into either the first memory 104 or the second memory 105 via the switch S1 for every H period portion, the other memory which is not undergoing the writing process produces via the switch S3 the signal Y of one H period immediately preceding the present H period. The third and fourth memories 106 and 107 also operate in the same manner.
The above-stated memory arrangement has been made for the purpose of time-base compressing one-H-period portions of the signals Y and C in a desired ratio between them. This arrangement is generally known as the double buffer method. More specifically, the one-H-period portion of the signal Y which is stored either at the first memory 104 or the second memory 105 and that of the signal C which is stored at the third memory 106 or the fourth memory 107 are produced during the next H period according to a clock frequency of {(M+N) / M} f.sub.Y {MHz} and a clock frequency of {(M+N) / N} f.sub.C {MHz} respectively. However, a point of time at which the signal C begins to be read out must be arranged to coincide with a point of time at which the signal Y ceases to be read out. In the formulas shown above:
M : N: Ratio in which the signals Y and C of FIG. 1 are time-base multiplexed
f.sub.Y : Clock frequency to be used in storing the signal Y in the memory
f.sub.C : Clock frequency to be used in storing the signal C in the memory
The signals Y and C are thus compressed by M / (M+N), and by N / (M+N) respectively.
Further, a switch S5 is arranged to have the signals Y and C time-base multiplexed in the manner as shown in FIG. 1. The connecting position of the switch S5 is at one terminal "a" thereof during a period from the start of reading the signal Y (or the end of reading the signal C) to the end of reading the signal Y (or the start of reading the signal C). During other periods, the connecting position of the switch S5 remains at the other terminal "b" thereof.
FIG. 3 is a timing chart showing the above-state operation. In FIG. 3, reference symbols Y' and C' respectively denote time compressed signals Y and C. A part (D) of FIG. 3 shows a multiplex signal obtained through the switching operation of the switch S5 which is as shown at a part (C) of FIG. 3.
Again referring to FIG. 2, an adder 110 is arranged to receive a horizontal synchronizing signal f.sub.H produced from the clock pulse generator 109 and the video signal which is time-base multiplexed and is coming via the switch S5. A signal produced from this adder 110 is frequency modulated by a frequency modulator 108 to be at an optimum recording level. Then, the adjusted signal is recorded through a head part 120 onto a recording medium which is not shown.
With the conventional electronic still picture camera arranged to perform recording as described in outline above, a reproduced picture can be obtained by carrying out a signal processing operation in a manner reverse to the operation described in the foregoing. As apparent from the foregoing, in recording or reproducing a video signal by a time-base multiplexing process, a memory arrangement is required for temporarily storing the signals Y and C. However, this requirement presents a problem which is serious especially in the case of such an apparatus as the electronic still picture camera that must be arranged in a compact size.